Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl core

Search list

[File Format] jiyuVHDLdeIPheyanzheng

Description: 摘要 探讨了IP 核的验证与测试的方法及其和 VHDL语言在 IC 设计中的应用 并给出了其在RISC8 框架 CPU 核中的下载实例．-Abstract IP nuclear testing and certification of the method and its VHDL and in IC Design and Application given its RISC8 framework in the CPU core downloaded example.
Platform: | Size: 118784 | Author: 赵天 | Hits:

[VHDL-FPGA-Verilog] 8051VHDL

Description: 一个C8051 内核的VHDL程序源代码-C8051 core of a VHDL source code
Platform: | Size: 420864 | Author: ydx | Hits:

[VHDL-FPGA-Verilog] PCI_target

Description: VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
Platform: | Size: 844800 | Author: citybus | Hits:

[SCM] mc8051_ug

Description: MC8051 IP Core Synthesizeable VHDL Microcontroller IP-Core-MC8051 Synthesizeable VHDL IP Core Microc ontroller IP-Core
Platform: | Size: 129024 | Author: 周仕凤 | Hits:

[Software Engineering] Designing_a_Multicycle_Processor--en

Description: 介绍怎样利用VHDL语言来实现一个多周期的处理器核心-on how to use VHDL to achieve more than one processor core cycle
Platform: | Size: 64512 | Author: 黎飞飞 | Hits:

[VHDL-FPGA-Verilog] DCT_vhdl

Description: IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed 1D IDCT core-- it ca n accept a continuous stream of 12-bit input word 's at a rate of-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP @ ML MPEG video-- the core is 100 % synthesizable
Platform: | Size: 10240 | Author: 陈朋 | Hits:

[VHDL-FPGA-Verilog] mdct.tar

Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767424 | Author: 陈朋 | Hits:

[Other] PCI_Target_ip

Description: pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci
Platform: | Size: 428032 | Author: zhouhong | Hits:

[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] FFT_CORE

Description: FFT算法的VHDL语言实现 可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
Platform: | Size: 29696 | Author: 紫蓝 | Hits:

[VHDL-FPGA-Verilog] mc8051_vhdl

Description: mcs51的vhdl IP核,是每个学习FPGA的必经之路，希望一起探讨-mcs51 the vhdl IP core, each is a must to learn FPGA, hoping to explore together
Platform: | Size: 394240 | Author: bluebluewind | Hits:

[Other] 8051_ip_core

Description: 8051微控制器的ip 核的vhdl源代码,其中包含了相应的测试程序.-8051 micro-controller ip nuclear vhdl source code, which contains the corresponding test procedures.
Platform: | Size: 339968 | Author: 大为 | Hits:

[Other] ptc

Description: PWM/TIMER/COUNTER VHDL IP core
Platform: | Size: 272384 | Author: hehilon | Hits:

[VHDL-FPGA-Verilog] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1024 | Author: lili | Hits:

[ARM-PowerPC-ColdFire-MIPS] sarm9beta

Description: arm9 架构简单core实现，可以综合，有实现步骤和说明，verilog代码编写。-arm9 core framework to achieve a simple, comprehensive, implementation steps and notes verilog code prepared.
Platform: | Size: 951296 | Author: blueli | Hits:

[Embeded-SCM Develop] adda_spi

Description: 这个源码是用altera公司的开发工具NIOS II IDE开发的基于软核处理器的AD、DA控制程序，通过spi 核控制AD、DA的时序，实现正弦波发送和接收-this source is altera company development tools NIOS II IDE- based soft-core Office JIMMY of AD and DA control procedures, spi nuclear control AD and DA timetables to achieve sine sending and receiving
Platform: | Size: 66560 | Author: zeng xuan | Hits:

[VHDL-FPGA-Verilog] ARM_core_VHDL

Description: 文件ARM_core_VHDL.rar 嵌入式arm核的vhdl语言描述.-document ARM_core_VHDL.rar Embedded arm of the nuclear vhdl language description.
Platform: | Size: 66560 | Author: 刘勇 | Hits:

[VHDL-FPGA-Verilog] mc8051V1.4

Description: 8051硬核源码（VHDL），具有全部VHDL代码、测试环境以及说明文档、综合脚本等完整的开发、验证环境，源代码通过ASIC投片，并得到不断完善-8,051 hard-core source code (VHDL), with all VHDL code, testing and documentation, environment, Comprehensive integrity of the script, such as development, certification, the source code for ASIC through films, and has been continually improved
Platform: | Size: 530432 | Author: 钟方 | Hits:

[File Format] ip-core-verification-based-on-vhdl

Description: 在万方数据库中载的，有参考价值，自然科学基金支持项目-in popular database contains the reference value, the Natural Science Fund to support projects
Platform: | Size: 379904 | Author: 王嘉 | Hits:
« 1 2 3 45 6 7 8 9 10 ... 30 »

CodeBus www.codebus.net